1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for fabricating a trench isolation without void problems.
2. Description of the Prior Art
Trench isolation (TI) has been gaining popularity for sub-micron technology and beyond to replace the traditional local oxidation of silicon (LOCOS) isolation process. However, as the design rule continues to shrink, gap filling a trench with a large aspect ratio (depth/width) has become increasingly challenging.
Referring to FIGS. 1A through 1C, the cross-sectional side views of a conventional method for fabricating a trench isolation are depicted in sequence.
Referring now to FIG. 1A, a cross-sectional view of the first step is schematically shown. FIG. 1A shows a semiconductor substrate 10 having a trench 12 that has an aspect ratio larger than 2. Preferably, a stop layer (not shown) for chemical mechanical polishing (CMP) could be formed on the semiconductor substrate 10.
Next, as shown in FIG. 1B, a oxide layer 14 having a void 16 is filled within the trench 12 by atmospheric pressure chemical vapor deposition (APCVD), using ozone and tetraethoxysilane (TEOS) as the main reactive gas. Thereafter, the oxide layer 14 is annealed for densification of the oxide layer 14.
Referring now to FIG. 1C, the oxide layer 14 is polished to leave the oxide layer 14a serving as the trench isolation.
As the aspect ratio of the trench becomes larger, the conventional APCVD method can not provide sufficient gap filling capacity. Therefore, it is necessary to form the trench isolation by high density plasma chemical vapor deposition (HPCVD). However, the cost of the apparatus will be very greatly increased.